In general, networks and computers operate in different manners. Networks operate by transferring data in streams and/or packets. Streams may be bit-sized, byte-sized, or otherwise broken down. Packets may be of relatively large size, such as 64, 512, or more bytes each. Computers operate by processing data, typically in well-defined small sizes, such as bytes (8 bits), words (16 bits), double words (32 bits) and so on. At the interface between a computer and a network, a translation or reorganization of data may be necessary. This may include assembling the bits of a stream into bytes, or breaking down a packet into double words for example. One component often used for this purpose is a FIFO (first-in-first-out) memory.
FIG. 1 illustrates an embodiment of a conventional circuit for processing data from a network. This circuit includes a FIFO, and may be used in the interface between a network and a computer. The circuit is used to receive data from a network interface, and provide that data to a processor which may assemble it in a manner suitable for use by a computer, or for transmission over another (different) network. The data is received and written into a FIFO, and is then read out from the FIFO into data registers. A reaccess compute module determines whether the next data in the FIFO is needed, or if the data already in one of the data registers needs to be accessed again (reaccessed). Whichever data is selected is then provided to the next stage in the processing circuitry.
Data 105 is received from a network at DEMUX (demultiplexer) 115, through a physical interface for example. Data 105 is of a predetermined data width. Channel select signal 120 determines which channel the data goes to through DEMUX 115. The output of DEMUX 115 is data and write control signal 125, which is steered to the proper FIFO 135 of FIFOs 130, based on channel select signal 120. The write control signal of data and write control 125 causes the data 125 to be written into FIFO 135. The data is then held in FIFO 135 until the next portion of the processing circuitry is ready for it.
The output data 140 of FIFO 135 (and of all of the FIFOs 130) is provided to register group 145 and to MUX (multiplexer) 160. The output data 140 is made available responsive to read control signal 180. The output data 140 may be stored in register A 150 and/or register B 155, also responsive to the read control signal 180. The outputs of register A 150 and register B 155 are made available to MUX 160.
Reaccess compute module 170 determines which of the inputs to MUX 160 should be selected as MUX output 165, and selects that input using source select signal 175. If the data that is to be provided to the next portion of processing circuitry is the data currently available from FIFO 135, that is selected, and it is read using read control signal 180. Otherwise, data previously read from FIFO 135, and currently in either of register A 150 or register B 155 is selected for reaccess. The output data 165 is then passed through as data 185 to the next portion of processing circuitry. Data 185 is also of a predetermined data width.
Having the register group 145 involves providing extra space and added circuitry (the MUX 160 for example), beyond what is normally involved in a FIFO. This is provided because the typical FIFO only provides data for reading once, and then moves on to the next data storage location in the FIFO. Thus, extra storage and data paths must be provided to allow for access of data from the FIFO a second time. Furthermore, the data may stay in the FIFO for long periods of time until it is accessed. However, a determination is made as to whether data must be reaccessed only when the data is first accessed, and not before. Typically, whether the data must be reaccessed or not is determined based on the effective output data width of data 105 as received from the network interface. The effective output data width may be determined by combining the data width of data 105 as received from the network interface with any data to be inserted prior to providing the data at the output. Such data to be inserted may be predicted at the time data 105 is available at the network interface, and may be inserted at the output stage of the FIFO for example (using additional logic not shown).